Pulse Code Modulation - Engineering Project

Pulse-code modulation (PCM) is a digital representation of an analog signal where the magnitude of the signal is sampled regularly at uniform intervals, then quantized to a series of symbols in a numeric (usually binary) code. PCM has been used in digital telephone systems and 1980s-era electronic musical keyboards. It is also standard in digital video, for example, using ITU-R BT.601. In the history of electrical communications, the earliest reason for sampling a signal was to interlace samples from different telegraphy sources, and convey them over a single telegraph cable. W.M. Miner, in 1903, used an electro-mechanical commutator for time-division multiplex of multiple telegraph signals, and also applied this technology to telephony. He obtained intelligible speech from channels sampled at a rate above 3500–4300 Hz: below this was unsatisfactory. This was TDM, but pulse-amplitude modulation (PAM) rather than PCM. The first transmission of speech by digital techniques was the SIGSALY vocoder encryption equipment used for high-level Allied communications during World War II from 1943. In 1943, the Bell Labs researchers who designed the SIGSALY system, became aware of the use of PCM binary coding as already proposed by Alec Reeves. In 1949 for the Canadian Navy's DATAR system, Ferranti Canada built a working PCM radio system that was able to transmit digitized radar data over long distances.

PCM TRANSMITTER

The message signal is passed through a band limiting low pass filter, which has a cut-off frequency Fc = W Hz. This will ensure that message signal will not have any frequency component higher than “W” Hz. This will eliminate the possibility of aliasing.The band limited signal is then applied to the Sample and Hold circuit where it is sampled at adequately high sampling rate. These samples are then subjected to the operation called “Quantization”. The Quantization is the process of approximation. The quantization is used to reduce the effect  of noise. The combined effect of sampling and quantization produces the quantized PAM at the quantizer output. The quantizer PAM pulses are then applied to an encoder which is basically an Analog to Digital converter. Each quantized level is then converted into N bit digital word by the A to D converter. The encoder output is then converted into the stream of pulses by Parallel to Serial Converter. Thus, at the PCM Transmitter output we get a train of digital pulses. The pulse generator produces a train of rectangular pulses with each pulses of duration ‘τ’ sec. The frequency of this signal is “Fs” Hz. This signal acts as a sampling signal for the Sample and Hold circuit block. The same signal acts as a “clock” signal for Parallel to Serial Converter. The frequency ‘Fs’ is adjusted to satisfy Nyquist criteria.

PCM RECEIVER (DECODER)

A PCM signal contaminated by noise is available at the receiver i/p. The regeneration circuit at the receiver will separate the PCM pulses from noise and will reconstruct the original PCM signal. The pulse generator has to operate in synchronization with that at the transmitter. Thus, at the regeneration circuit o/p, we get the ‘clean’ PCM signal. The reconstruction of PCM signal is possible due to the digital nature of the PCM signal. The reconstructed PCM signal is then passed through a serial to parallel converter. Output of this block is then applied to the decoder. The decoder is a D to A converter which performs exactly the opposite action of the encoder. The decoder o/p is the sequence of quantized multilevel pulses. The quantized PAM signal is thus obtained at the o/p of the decoder. This quantized PAM signal is passed through a LPF to recover the analog signal, x(t). The LPF is called as the reconstruction filter and its cut off frequency is equal to the message bandwidth W.

Sampling Theorem

Any continuous signal x(t) can be  completely represented in its sampled form and can be recovered back from the sampled form if the sampling frequency fs ≥ 2Bwhere B is the maximum component present in the signal.

Here, our input signal frequency (max) is 3.4 KHz. So, from sampling theorem, sampling frequency should be greater than 2*3.4 k = 6.8 KHz. We have chosen Fs = 7.812 KHz.

In digital signal processing, quantization is the process of approximating ("mapping") a continuous range of values (or a very large set of possible discrete values) by a relatively small ("finite") set of ("values which can still take on continuous range") discrete symbols or integer values. For example, rounding a real number in the interval [0,100] to an integer. In other words, quantization can be described as a mapping that represents a finite continuous interval I = [a,b] of the range of a continuous valued signal, with a single number c, which is also on that interval. For example, rounding to the nearest integer (rounding ½ up) replaces the interval [c − .5,c + .5) with the number c, for integer c. After that quantization we produce a finite set of values which can be encoded by binary techniques for example. In signal processing, quantization refers to approximating the output by one of a discrete and finite set of values, while replacing the input by a discrete set is called discretization, and is done by sampling: the resulting sampled signal is called a discrete signal (discrete time), and need not be quantized (it can have continuous values). To produce a digital signal (discrete time and discrete values), one both samples (discrete time) and quantizes the resulting sample values (discrete values).

TRANSMITTER DESIGN

DESIGN OF CLOCK GENERATOR

The crystal oscillator has very stable output frequency which does not change much with the change in temperature. Therefore the crystal oscillator is used to produce the clock signal for the microprocessor. Such an oscillator is called as the crystal clock. The electrical equivalent of crystal is a series resonant circuit. It frequency is given by

f=1/2π (LC) ^1/2

Crystal clock is made up of three invertors, a capacitor and two resistors along with the crystal. The three invertors act as inverting amplifiers. The invertors 1&2 together form a two stage amplifier with an overall phase shift of 360 between points X &Y. Capacitor c is used for ac coupling between two invertors. The crystal is connected from the output of invertor 2 to the input of invertor 1. Through the crystal a part of output is returned back to input. Thus feedback is given through crystal. The type of feedback is positive because points X &Y are in phase and the crystal is equivalent to resistance R at its resonant frequency.Thus crystal acts as a resistive feedback network and does not introduce any phase shift. The Barkhausen criterion is thus satisfied and the circuit starts oscillating at the resonant frequency of the crystal. Invertor 3 acts as inverting buffer amplifier and output voltage is obtained at its output. The output has a rectangular shape due to use of logic gates.

The CD4017BC is ‘divide by 10’ Johnson counter IC with 10 decoded output and carry output bit. These counters are cleared to their 0 count by logical 0 on their reset line. These counters are advanced on positive edge of clock signal. Each decoded output remains high for 1 full clock cycle. The carry output completes 1 full cycle for every 10/8 clock input cycle and s used as ripple carry signal for any succeeding stages.

Design of Low pass filter

Using second order low pass filter for design. PCM is generally used to encode the voice data i.e. the data having the frequency ranging from 0Hz to 3.4 kHz. Hence, the cut off frequency of the filter is 3.4 kHz. We are using the second order low pass Butterworth filter because it shows a response which rolls at a rate of -40db/decade. This rate is double the rate of the first order filter.

The cut off frequency F_c is determined by R2, C2, R3 and C3 as follows

F_c=1/ (2π√R2R3C2C3)

The pass band gain of the filter is determined by values of Rf and R1.

Avf = 1 + ( Rf)/R1

And  Avf=3-α.

ADC DESIGN

The Sample and Hold circuit, Quantizer and Encoder circuits are integrated in

Analog to Digital converter IC

The ADC0808, ADC0809 data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital converter,8-channel multiplexer and microprocessor compatible control logic. The 8-bit A/D converter uses successive approximation as the conversion technique. The converter features high impedance chopper stabilized comparator, a 256R voltage divider with analog switch tree and a successive approximation register. The 8-channel multiplexer can directly access any of 8-single-ended analog signals.

CLOCK

The clock of the ADC is operated at 1MHz.

DESIGN OF LATCH

The code words generated at the output of ADC should be latched before they are transmitted serially.

Use 3-STATE Octal D-Type Transparent Latches

These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

PARALLEL TO SERIAL CONVERTER DESIGN

Using IC 74151 i.e.8:1 MUX

The 8 output bits of the ADC are applied to the inputs of the MUX. However, the select Lines are operated by the 3 bit (Modulo-7) counter. Therefore, each of the bit in the code is available at the output line of the MUX in the serial manner. The Modulo-7 counter is designed using IC 4040 i.e. Binary Ripple Counter.

RECEIVER

SERIAL TO PARALLEL CONVERTER

IC 74198 is 8 bit R/L shift registers.  It features synchronous parallel load, hold, shift right, shift left modes as determined by selects (S0 & S1) inputs. State changes are initiated by rising edge of clock pulse. An asynchronous master reset (MR) input overrides all other inputs &clear register. The 198 is useful for serial-parallel, serial-serial, parallel-serial, parallel-parallel register transfer.

At the output of the serial to parallel converter, we get the 8-digit PCM word. The clock for this IC is derived from point D of the clock generation circuit.