This project deals with the control circuit for the switched mode power supply and is a combination of a microcontroller and a FPGA. The microcontroller will be doing the user interface, communication function and the FPGA will carry out the switching function. The idea behind partitioning the functions into FPGA and controller is to have a deterministic control system and use the inherent parallelism offered by the FPGA to implement the control PID loops.
SPECIFICATIONS
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Power Wattage =10KW
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Voltage Rating = 1000V
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Current Rating = 10A
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Topology - Full Bridge
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Switching Elements - IGBT
The project is to build the SMPS controller
on a Field Programmable Gate Array i.e., FPGA. To write the VHDL code for the
SMPS controller, we had to first understand the working of a switched mode
power supply and then identify the parameters required to control it. So, the
outline that we found out about Switched Mode Power Supply is as follows:
i) Switched Mode Power Supply: A
switched-mode power supply or SMPS is an electronic power supply unit (PSU)
that incorporates a switching regulator. While a linear regulator maintains the
desired output voltage by dissipating excess power in a "pass" power
transistor, the SMPS rapidly switches a power transistor between saturation
(full on) and cutoff (completely off) with a variable duty cycle whose average
is the desired output voltage. The resulting rectangular waveform is low-pass
filtered with an inductor and capacitor. The main advantage of this method is
greater efficiency because the switching transistor dissipates little power in
the saturated state and the off state compared to the semi conducting state
(active region). Other advantages include smaller size and lighter weight (from
the elimination of low frequency transformers which have a high weight) and
lower heat generation from the higher efficiency.
Comparison of a Linear power supply and a
switched-mode power supply
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Parameters
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Linear power supply
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Switching power
supply
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Notes
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Size and weight
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Huge due to low operating frequency ( mains
power frequency is at 50 or 60 Hz)
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Smaller due to higher operating frequency
(typically 50 kHz - 1 MHz)
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A transformer's power handling capacity of given
size and weight increases with frequency provided that hysteresis losses can
be kept down. Therefore, higher operating frequency means either higher
capacity or smaller transformer.
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Parameters
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Linear power supply
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Switching power
supply
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Notes
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Output voltage
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Output can only produce a positive/negative
voltage which varies depending on loading.
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Output is able to produce a voltage lower,
higher or even negative to the input voltage with superior regulation.
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A SMPS can usually cope with wider
variation of input before the output voltage changes.
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Complexity
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Consists of a voltage regulating IC or
discrete circuit and a noise filtering capacitor.
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Consists of a controller IC, one or several
power transistors and diodes as well as a power transformer, inductors, and
filter capacitors.
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Multiple voltages can be generated by one
transformer core. For this SMPSs have to use duty cycle control. Both need a
careful selection of their transformers. Due to the high operating
frequencies in SMPSs, the stray inductance and capacitance of the printed
circuit boards traces become important.
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Radio Frequency
Interference
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No interference produced, except
possibility of mains hum induction into unshielded cables.
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EMI/RFI produced due to the current being
switched on and off sharply. Therefore, EMI Filters and RF Shielding are
needed to reduce the disruptive interference.
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Long wires between the components may
reduce the high frequency filter efficiency provided by the capacitors at the
inlet and outlet.
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Unregulated PSUs may have a small amount of
AC "riding on" the DC component at twice the main frequency
(100-120 Hz). This can cause an audible mains
hum in audio equipment or unexpected brightness ripples or other banded -distortions in analog security cameras.
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Noisier due to the switching frequency of
the SMPS. An unfiltered output may cause glitches in digital circuits or
noise in audio circuits.
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This can be suppressed with capacitors and
other filtering equipment in the output stage.
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Causes harmonic distortion to the input AC,
but no high frequency noise.
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Very low cost SMPS may couple electrical
switching noise back onto the mains power line, causing interference with A/V
equipment connected to the same phase.
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This can be prevented if a (properly
earthed) EMI/RFI filter is connected between the input terminals and the
bridge rectifier.
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Risk of equipment destruction
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Very low, unless a short occurs between the
primary and secondary windings or the regulator fails by shorting internally.
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Capable of destroying input stages in
amplifiers due to the floating voltage being above the base-emitter breakdown
voltage of the transistor, causing the transistor's gain to drop and noise
levels to increase.
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The floating voltage is caused by
capacitors bridging the primary and secondary sides of the power supply. A
connection to earthed equipment will cause a momentary (and potentially
destructive) spike in current at the connector as the voltage at the
secondary side of the capacitor equalizes to earth potential.
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ii) FPGA:
The FPGA is an
integrated circuit that contains many (64 to over 10,000) identical logic cells
that can be viewed as standard components.
Each logic cell can independently take on any one of a limited set of personalities. The individual cells are interconnected by a
matrix of wires and programmable switches.
A user's design is implemented by specifying the simple logic function
for each cell and selectively closing the switches in the interconnect
matrix. The array of logic cells and
interconnects form a fabric of basic building blocks for logic circuits. Complex designs are created by combining
these basic blocks to create the desired circuit.
FPGA's function is
defined by a program written by someone other than the device
manufacturer. Depending on the
particular device, the program is either 'burned' in permanently or
semi-permanently as part of a board assembly process, or is loaded from an
external memory each time the device is powered up. This user programmability gives the user
access to complex integrated designs without the high engineering costs.
Individually defining
the many switch connections and cell logic functions would be a daunting
task. Fortunately, this task is handled
by special software. The software
translates a user's schematic diagrams into hardware description language
code.Most of the software packages have hooks to allow the user to influence
implementation, placement and routing to obtain better performance and
utilization of the device.
FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of conventional
ASICs. Also, FPGA programmability permits design upgrades in the field with no
hardware replacement necessary, an impossibility with ASICs.
ADVANTAGES OF FPGA
- There is no wait from completing the design to obtain a working chip. The design can be programmed into FPGA and tasted immediately.
- FPGAs are excellent prototyping vehicle. When they are used in final design, the jump from prototype to product is much smaller and easier to negotiate.
- The same FPGA can be used in several different designs, reducing inventor costs.
- Non recursive engineering cost reduces.
- Time to market the product is less.
- It is used in DSP design as major FPGA vendors offer DSP builder tools that combine the algorithm development, simulation, and verification capabilities of Matlab and Simulink with synthesis, simulation, and place and route.
- Designing FPGA tools is often less expensive than custom VLSI tools.
- A newer category of FPGA called “PLATFORM FPGAs includes several different types of structures so that each part of a large system can be efficiently implemented on the type of structure best suited to it. A “PLATFORM FPGA typically includes a CPU so that some functions canbe run in software. It can also include specialized but logic.
ADVANTAGES OF FPGA
OVER PROCESSORS
- Programming an FPGA is very different from programming a microprocessors. A microprocessor is a stored program computer which includes both a CPU and a separate memory that stores instruction and data. The FPGA’s program is interwoven into the logic structure of the FPGA. An FPGA does not fetch instructions—the FPGA’s programming directly implements logic functions and interconnections.
- FPGAs are reconfigurable. System using FPGA can also be reprogrammed on the fly during the system operation.. this allows one piece of hardware to perform several different functions. Of course those function cannot be performed at the same time, but reconfigurability can be very useful when the system operates in different modes.
DISADVANTAGES
OF FPGA
- FPGAs are not costom parts so they aren’t as good at any particular function as a dedicated chip designed for the application.
- They are generally slower and burn more power than custom logic.
- They are relatively expensive than the custom design chips which are cheaper.
iii) SPARTAN:
The Spartan-3 family of
Field-Programmable Gate Arrays is specifically designed to meet the needs of
high volume, cost-sensitive consumer electronic applications. The eight-member
family offers densities ranging from 50,000 to five million system gates on a
single chip.
The Spartan-3 builds in the
success of the earlier Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of I/Os, and the
overall level of performance improving clock management function. Because of
their exceptionally low cost, Spartan3 is ideally suited for wide range of
consumer electronic applications, including broadband access, home networking
and digital television equipment.
Spartan-3 FPGAs are programmed by
loading configuration data into static memory cells that collectively control
all functional elements and routing resources.
The Spartan-3 family is a superior
alternative to mask programmed ASICs i.e. Application Specific Integrated C
- Linear opto-isolation and Scalar Block:
The
input voltage and current supplied to SMPS and the output voltage and current
obtained from the smps are sensed and given to the Opto-isolation block for
isolating the high power smps circuit from the low power controller circuit.
.The voltage level is also scaled to 5V according to the controller circuit
specification.
- ADC:
The
FPGA is interfaced to four high speed 16 bit SAR parallel ADCs which convert
the sensor’s analog output into digital output which is then given to the FPGA.
- Microcontroller:
The
FPGA has an interface to the microcontroller which can address up to 255
parameters inside the FPGA.
- FPGA:
- All the control actions are done by the FPGA. The FPGA is carrying out the switching function part. FPGA is a combination of PID control block and complementary PWM generation.
- PID loop has voltage, current and power control.
- FPGA handles arc suppression. The FPGA has an interface to 4 IGBT and their respective error handling functions.
FPGA
has following blocks
Pulsar Block
The output of pulsar block
is a pulsating DC having frequency in the range of 1 KHz to 20 KHz with
variable duty cycle, both of which are programmable. The pulsar block output drives
the IGBT connected in series with the power supply. The pulsar block is
interfaced to the ARC Suppression block, the IGBT error handling block, the
DATA Distribution block and the Digital Clock Manager.
The signals to this block are
PWM Generator Block
The PWM GENERATOR BLOCK
outputs the basic PWM waveforms at the basic PWM frequency of 20-KHz. This
block generates complementary PWM signals with variable pulse width to drive four
IGBTs in a full bridge format. This block is interfaced to the DPID block from
which it receives the error signal which decides the pulse width, and outputs four
PWM signals to the IGBT error handling block for onward transmission to the
IGBTs. It also receives signals from the ARC SUPPRESSION BLOCK and the DIGITAL
CLOCK MANAGER.
The signals to this block are
IGBT Error Handling Block
The IGBT ERROR HANDLING
BLOCK receives driving signals from the PWM GENERATOR BLOCK and the PULSAR
BLOCK. It is also interfaced to the IGBT driver cards to get IGBT ERROR STATUS
and provides signals for resetting the IGBT driver card.
The signals to this block are
DPID
Block
The DPID block is the main
PID control block. It gets inputs from the data distribution block. It is
interfaced to four Analog to Digital Converters and gives output to the PWM
GENERATOR BLOCK as error signal. The main function of the DPID block is to
compute the error signal based on set values which it receives from the Data
distribution block and the actual values of voltage and current from the ADCs.
It supplies the current information to the ARC SUPPRESSION BLOCK and also performs
the function of input mains sensing.
The signals to this block are
Arc Suppression Block
The ARC SUPPRESSION BLOCK
senses the output current it receives from the DPID block and compares it with
values received from the DATA DISTRIBUTION BLOCK. On detection of a match the ARC
DETECT signal which is used by the various blocks stays active for a duration
defined by ARC STRETCH time from DATA distributor block. This block also keeps
track of how many current overshoots happen in a given time and will generate a
trip signal if this count is exceeded. The COUNT comes from the DATA
distributor block.
The signals to this block are
The DATA DISTRIBUTION BLOCK
is the interface between the external microcontroller and the rest of the FPGA.
It gathers all operating information from the microcontroller and supplies this
to the various blocks. Conversely it gathers status information from all the
blocks and is made available to the microcontroller on demand. The
microcontroller interface is in the form of a data bus, address bus, read write
control, FPGA reset and FPGA READY signals.
Digital Clock Manager
The DCM is a utility used in
the FPGA to basically generate clock signals used by the various blocks. It has
a basic 40MHz oscillator as an input and generates two clock signals CLK40 and
CLK80 which are used by various blocks.
The signals to this block are
COMPONENT SELECTION
There are many choices when it comes to component
selection so we wish to elaborate why we have chosen only these particular
ones.
We have based the selection on the following factors:
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Speed to process a data
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Data/address bus
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Memory capacity
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Flexibility
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Space required for the mounting
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Comfort and previous knowledge of the
component.
REQUIREMENTS OF PROJECT
- Current project requires very high processing speed integrates circuits.As FPGA does not fetch instructions—the FPGA’s programming directly implements logic functions and interconnections time it takes to procces a data is less.
- Spartan 3 as it has dedicated multiplier blocks.
- Xilinx ISE 9.1 Software.
§ --ISESimulator
§ --ModelSim© Xilinx Edition-III.
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